1. Field of the Invention
The present invention generally relates to a DRAM with a dopant stop layer and a method of fabricating the DRAM with the dopant stop layer. In particular, the present invention is directed to a DRAM of longer data retention time and a method of fabricating the DRAM of longer data retention time.
2. Description of the Prior Art
A dynamic random access memory (DRAM) is an integrated circuit composed of many memory units. The DRAM is also one of the most popular main volatile memories used in modern computing devices. Each memory unit in the DRAM is composed of a metal oxide semiconductor (MOS) in series with a capacitor (also known as a single bit) or two capacitors (also known as double bits), wherein each MOS transistor and capacitor are electrically connected to several word lines and bit lines to further locate the address of each memory unit.
Longer data retention time is always a challenge for high quality DRAMs. With continuous shrinkage of component dimensions and improvement in processing speeds, it is becoming more and more difficult to keep data retention time at adequate levels. Accordingly, data retention time requires constant improvement.
Traditionally, boron dopant is used to adjust a threshold voltage of the MOS transistor in a DRAM process. Because boron dopant is susceptible to diffuse and form boron clusters in the presence of heat, however, electric leakage may be an unwanted consequence. The current solution to reduce boron clusters is to lower the concentration of the boron dopant used or to employ a lower temperature for the rapid thermal annealing, but these solutions respectively lead to a lower transistor threshold voltage or an NMOS electric problem.